x86: Intel MID platforms has no microcode update

There is no microcode update available for SoCs used on Intel MID
platforms.

Use conditional to bypass it.

Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 988073cc7953f188cf1ffc7758263df83934b437..cfd9bb447b8bcb7035fe2acc6f9efebe09d08242 100644 (file)
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -248,7 +248,8 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
        if (!stack)
                return -ENOMEM;
        params->stack_top = (u32)(stack + size);
-#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
+       !defined(CONFIG_INTEL_MID)
        params->microcode_ptr = ucode_base;
        debug("Microcode at %x\n", params->microcode_ptr);
 #endif